Dasharo coreboot port for NovaCustom MTL dGPU models

[mkopec]

The problem you're addressing (if any)

The dGPU boards are different to iGPU models and require a separate coreboot port. Vast portions are common but a lot of things are different, as the board is physically different.

Describe the solution you'd like

Add coreboot port for NovaCustom models with dGPU graphics.

• [x] GPIO configuration - already done
• [x] devicetree - mostly done, need to verify dGPU config
• [x] FSP config
• [ ] audio, smart amp
• [x] dGPU power sequencing
• [ ] dGPU ACPI code for Optimus power management
• [ ] Verify display mux functionality on coreboot side

Where is the value to a user, and who might that user be?

No response

Describe alternatives you've considered

No response

Additional context

No response

[mkopec]

coreboot allocates resources for the dGPU device above 4G:

[18:34:21.580] [DEBUG]  PCI: 00:01:00.0 10 <- [0x0000000098000000 - 0x0000000098ffffff] size 0x01000000 gran 0x18 mem
[18:34:21.593] [DEBUG]  PCI: 00:01:00.0 14 <- [0x0000000400000000 - 0x00000005ffffffff] size 0x200000000 gran 0x21 prefmem64
[18:34:21.601] [DEBUG]  PCI: 00:01:00.0 1c <- [0x0000000600000000 - 0x0000000601ffffff] size 0x02000000 gran 0x19 prefmem64
[18:34:21.613] [DEBUG]  PCI: 00:01:00.0 24 <- [0x0000000000002000 - 0x000000000000207f] size 0x00000080 gran 0x07 io
[18:34:21.621] [DEBUG]  PCI: 00:01:00.0 30 <- [0x0000000099000000 - 0x000000009907ffff] size 0x00080000 gran 0x13 romem
[18:34:21.634] [DEBUG]  PCI: 00:01:00.1 10 <- [0x0000000099080000 - 0x0000000099083fff] size 0x00004000 gran 0x0e mem

Even though CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is set

edk2 throws an assert here:

[18:34:31.689]   Support/Attr: 7001F / 7001F
[18:34:31.689]     DmaAbove4G: No
[18:34:31.693] NoExtConfSpace: No
[18:34:31.693]      AllocAttr: 0 ()
[18:34:31.697]            Bus: 0 - 2F Translation=0
[18:34:31.701]             Io: 2000 - EFFF Translation=0
[18:34:31.705]            Mem: 80000000 - 601FFFFFF Translation=0
[18:34:31.709]     MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
[18:34:31.713]           PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
[18:34:31.718]    PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0

[18:34:31.726] DXE_ASSERT!: [PciHostBridgeDxe] /home/coreboot/coreboot/payloads/external/edk2/workspace/Dasharo/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c (141): Bridge->Mem.Limit < 0x0000000100000000ULL

[18:34:31.742] DXE_ASSERT!: [PciHostBridgeDxe] /home/coreboot/coreboot/payloads/external/edk2/workspace/Dasharo/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c (481): RootBridge != ((void *) 0)

there's an assumption in edk2 that coreboot assigns everything below 4G: https://github.com/Dasharo/edk2/blame/dasharo/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c#L49

obviously it's not true anymore.

[mkopec]

^ issue fixed by https://github.com/Dasharo/edk2/pull/161

[mkopec]

I've managed to rework google's code for Nvidia power management to work for our boards. There were some differences:

• they did pwr sequencing of each pwr rail, themselves, we have fewer signals to worry about, but I still had to rework the power sequencing code
• they didn't have to worry about windows (I had to add PCI SSID restore)
• PMC IPC interface for srcclk control was dropped in MTL, needed to change to P2SB access

There's still some suspicious throttling probably because we don't have D-notifier support on EC side. I'll just try to force highest D-level for max performance for now.

Also Nvidia GOP driver that loads in edk2 automatically, causes internal graphics to break in Windows. Not sure what that's about, I ended up disabling option ROM loading altogether. This means HDMI and second USB-C port video outputs won't work in firmware (they still work just fine in OS)

[BeataZdunczyk]

Closing this issue as we have moved the NVIDIA display mux to a separate issue: https://github.com/Dasharo/dasharo-issues/issues/1024