learn-fpga
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BrunoLevy
Learning FPGA, yosys, nextpnr, and RISC-V
learn-fpga/FemtoRV$ make ICESUGAR ... make[2]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE/CRT' ==== Generated femtorv32 libs. make[1]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE' make: *** No rule to make target 'FIRMWARE/firmware.hex', needed by 'ICESUGAR.synth'. Stop.
I tried to run through this tutorial https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FOMU.md and I found it doesn't work with my FOMU, which is the very first version, v0.0, here https://workshop.fomu.im/en/latest/requirements/hardware.html it is named "Hacker"....
Coming back to this after a couple of months and installing new versions of everything (Litex/yosys/nextptr) from github, and now it won't compile (yosys error): ``` ~/learn-fpga/LiteX$ python3 -m boards.radiona_ulx3s_ex...
Hi, Thank you for building this awesome project, I am trying to build the softcore for Icestick and run an example program but I am not able to get any...
I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not...
What I am asking for is some details on how to use system bus backpressure signals, so I can integrate quark into my FPGA synthesis and Verilator simulation (ISA tests)....
FuseSOC
Would be good to - make FemtoRV32 and the cores in RTL/DEVICES/ available through FuseSoc, - use other FuseSoc cores in FemtoSoc
Hi to all Thanks for this compact package, I greatly appreciate that i got everything running on my icebreaker board with basically two to three commands. I am now searching...
I had to do some tweaks to install the open-source toolchain for the Arty board that I'd like to share, and hopefully the [wiki](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/toolchain_arty.md) can be updated $PRJXRAY and $LEARN_FPGA...
