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BrunoLevy
Add Sipeed Tangnano9k and Tangnano20k boards
Necessary changes have been made to support these two boards with GOWIN chips, but still WIP.
But I'm stuck on the fact that iverilog doesn't like registers being declared after they are used. Although it's possible that I'm doing something wrong. Although in processor files registers are actually described much later than use:
https://github.com/yrabbit/learn-fpga/blob/5bb5c5e5490d31366e41e16d8b5822a62d70254a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v#L63
https://github.com/yrabbit/learn-fpga/blob/5bb5c5e5490d31366e41e16d8b5822a62d70254a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v#L198
~/src/learn-fpga/FemtoRV$ make TANGNANO9K
BOARD=tangnano9k TOOLS/make_config.sh -DTANGNANO9K
./PROCESSOR/femtorv32_quark.v:63: error: Unable to bind wire/reg/memory `instr['sd11:'sd7]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:63: error: Unable to elaborate r-value: instr['sd11:'sd7]
./PROCESSOR/femtorv32_quark.v:68: error: Unable to bind wire/reg/memory `instr['sd14:'sd12]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:68: error: Unable to elaborate r-value: (8'd1)<<(instr['sd14:'sd12])
./PROCESSOR/femtorv32_quark.v:71: error: Unable to bind wire/reg/memory `instr['sd31]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:71: error: Unable to bind wire/reg/memory `instr['sd30:'sd12]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:72: error: Unable to bind wire/reg/memory `instr['sd31]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:72: error: Concatenation/replication may not have zero width in this context.
./PROCESSOR/femtorv32_quark.v:72: error: Unable to bind wire/reg/memory `instr['sd30:'sd20]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
./PROCESSOR/femtorv32_quark.v:72: error: Concatenation/replication may not have zero width in this context.
./PROCESSOR/femtorv32_quark.v:72: error: Unable to elaborate r-value: {{'sd21{instr['sd31]}}, instr['sd30:'sd20]}
./PROCESSOR/femtorv32_quark.v:74: error: Unable to bind wire/reg/memory `instr['sd31]' in `FemtoRV32'
./PROCESSOR/femtorv32_quark.v:198: : A symbol with that name was declared here. Check for declaration after use.
@yrabbit mind me taking a look? I was gonna fork the original repo to add 9k/20k projects, but I can work from yours
Absolutely no objections are even welcomed. Let me know when you pick it up and I'll close this Draft.
@yrabbit I've been playing with all the stepXX.v files for Tang Nano 9K and I found an issue unrelated to the issue you are having with iverilog
So, in step17.v, @BrunoLevy starts memory mapping peripherals, and he extends the RAM to 6kB. If you try to synthesize with yosys, then you'll run out of memory because the synth is trying to infer reg [31:0] MEM [0:1535]; into RAM16SDP4 shadow SSRAM blocks, and there are only 270 blocks.
Info: Device utilisation:
Info: VCC: 1/ 1 100%
Info: IOB: 9/ 274 3%
Info: LUT4: 8441/ 8640 97%
Info: OSER16: 0/ 80 0%
Info: IDES16: 0/ 80 0%
Info: IOLOGICI: 0/ 276 0%
Info: IOLOGICO: 0/ 276 0%
Info: MUX2_LUT5: 1296/ 4320 30%
Info: MUX2_LUT6: 392/ 2160 18%
Info: MUX2_LUT7: 186/ 1080 17%
Info: MUX2_LUT8: 71/ 1080 6%
Info: ALU: 182/ 6480 2%
Info: GND: 1/ 1 100%
Info: DFF: 201/ 6480 3%
Info: RAM16SDP4: 800/ 270 296%
Info: BSRAM: 0/ 26 0%
Info: ALU54D: 0/ 10 0%
Info: MULTADDALU18X18: 0/ 10 0%
Info: MULTALU18X18: 0/ 10 0%
Info: MULTALU36X18: 0/ 10 0%
Info: MULT36X36: 0/ 5 0%
Info: MULT18X18: 0/ 20 0%
Info: MULT9X9: 0/ 40 0%
Info: PADD18: 0/ 20 0%
Info: PADD9: 0/ 40 0%
Info: GSR: 1/ 1 100%
Info: OSC: 0/ 1 0%
Info: rPLL: 1/ 2 50%
Info: BUFG: 0/ 22 0%
Info: DQCE: 0/ 24 0%
Info: DCS: 0/ 8 0%
Info: CLKDIV: 0/ 8 0%
Info: CLKDIV2: 0/ 16 0%
Info: Running custom HCLK placer...
Info: Placed 0 cells based on constraints.
ERROR: Unable to place cell 'RAM.MEM.0.546', no BELs remaining to implement cell type 'RAM16SDP4'
0 warnings, 1 error
What we'd like, is to infer SP-BSRAM instead.
I guess because of this code block:
if(mem_wmask[0]) MEM[word_addr][ 7:0 ] <= mem_wdata[ 7:0 ];
if(mem_wmask[1]) MEM[word_addr][15:8 ] <= mem_wdata[15:8 ];
if(mem_wmask[2]) MEM[word_addr][23:16] <= mem_wdata[23:16];
if(mem_wmask[3]) MEM[word_addr][31:24] <= mem_wdata[31:24];
the synth uses shadow RAM to keep a READ version of MEM before writing back, bacause of the code being implemented as byte-writeable.
I checked SP-BSRAM and doesn't support writing bytes into 32-bit words, so that functionality needs to be added in the controller. Maybe using the functionality READ-before-WRITE of the SP-BSRAM?
Well, no such problem has been noticed - yosys uses BSRAM properly. And it seems to have been working for a long time, try the master branch of yosys.
Mine is Yosys 0.43+11 (git sha1 81df8557d94c7e1ff734f2f90adcf00a67632302, c++ 8.3 -O2 -fno-strict-aliasing -fPIC -Os)
rabbit@fly ~/var/learn-fpga_GOWIN/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV% BOARDS/run_tangnano9k.sh step17.v
Info: Using uarch 'gowin' for device 'GW1NR-LV9QN88PC6/I5'
Info: Reading constraints...
Info: Create constant nets...
Info: Modify LUTs...
Info: Pack IOBs...
Info: Pack diff IOBs...
Info: Pack IO logic...
Info: Pack DESER16 logic...
Info: Pack GSR...
Info: Pack HCLK cells...
Info: Pack wide LUTs...
Info: Packed MUX2_LUT8:19, MUX2_LU7:9, MUX2_LUT6:71, MUX2_LUT5:172
Info: Pack ALUs...
Info: Pack PLL...
Info: Pack RAMs...
Info: Pack BSRAMs...
Info: Pack DSP...
Info: Pack INV...
Info: Pack buffered nets...
Info: Pack UserFlash cells...
Info: Pack DQCE cells...
Info: Pack DCS cells...
Info: Checksum: 0x6c88cd50
Info: Device utilisation:
Info: VCC: 1/ 1 100%
Info: IOB: 9/ 274 3%
Info: LUT4: 1717/ 8640 19%
Info: OSER16: 0/ 80 0%
Info: IDES16: 0/ 80 0%
Info: IOLOGICI: 0/ 276 0%
Info: IOLOGICO: 0/ 276 0%
Info: MUX2_LUT5: 502/ 4320 11%
Info: MUX2_LUT6: 165/ 2160 7%
Info: MUX2_LUT7: 47/ 1080 4%
Info: MUX2_LUT8: 19/ 1080 1%
Info: ALU: 182/ 6480 2%
Info: GND: 1/ 1 100%
Info: DFF: 169/ 6480 2%
Info: RAM16SDP4: 32/ 270 11%
Info: BSRAM: 4/ 26 15%
Info: ALU54D: 0/ 10 0%
Info: MULTADDALU18X18: 0/ 10 0%
Info: MULTALU18X18: 0/ 10 0%
Info: MULTALU36X18: 0/ 10 0%
Info: MULT36X36: 0/ 5 0%
Info: MULT18X18: 0/ 20 0%
Info: MULT9X9: 0/ 40 0%
Info: PADD18: 0/ 20 0%
Info: PADD9: 0/ 40 0%
Info: GSR: 1/ 1 100%
Info: OSC: 0/ 1 0%
Info: rPLL: 1/ 2 50%
Info: BUFG: 0/ 22 0%
Info: DQCE: 0/ 24 0%
Info: DCS: 0/ 8 0%
Info: CLKDIV: 0/ 8 0%
Info: CLKDIV2: 0/ 16 0%
@fjpolo By the way parts of these tutorials are included in the apicula supply in the examples, if you look in the examples/himbaechel directory.
femto-riscv-15.v
femto-riscv-16.v
femto-riscv-18.v
There are no BSRAM tricks in there - everything just compiles.
https://github.com/YosysHQ/apicula/blob/master/examples/himbaechel/femto-riscv-18.v
@yrabbit thank you very much kind sir!
Edit: Actually @yrabbit what's the correct way to Make the projects apicula/examples/himbaechel/femto-riscv-xx.v?
I'm using the following script I made:
DEVICE='GW1NR-LV9QN88PC6/I5'
BOARD='tangnano9k'
BOARD_FREQ=27
CPU_FREQ=40
BAUD_RATE=115200
PROJECT=$1
# FIRMWARE='riscv-dsp-firmware/mult9x9.hex'
#
yosys -DLEDS_NR=6 -DCPU_FREQ=$CPU_FREQ -DBAUD_RATE=$BAUD_RATE -DFIRMWARE=$FIRMWARE -DINV_BTN=0 -p "read_verilog $PROJECT.v; synth_gowin -json $PROJECT-$BOARD-synth.json"
nextpnr-himbaechel --json $PROJECT-$BOARD-synth.json --write $PROJECT-$BOARD-pnr.json --device $DEVICE --vopt family=GW1N-9C --vopt cst=$BOARD.cst
gowin_pack -d GW1N-9C -o pack.fs $PROJECT-$BOARD-pnr.json
sudo openFPGALoader -b $BOARD pack.fs
But I'm still getting ERROR: Unable to place cell 'RAM.MEM.0.546', no BELs remaining to implement cell type 'RAM16SDP4' so I guess I'm still missing something for femto-riscv-18.v.
@fjpolo
maybe it's the Yosys version. I would like to have a look at your out.log file - there is a piece after synthesis:
Removed 0 unused modules.
2.30. Printing statistics.
=== top ===
Number of wires: 2376
Number of wire bits: 8425
Number of public wires: 2376
Number of public wire bits: 8425
Number of ports: 5
Number of port bits: 10
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 2601
$scopeinfo 4
ALU 159
DFF 6
DFFE 110
DFFR 4
DFFRE 37
DFFSE 1
GND 1
IBUF 3
LUT1 436
LUT2 136
LUT3 391
LUT4 573
MUX2_LUT5 482
MUX2_LUT6 153
MUX2_LUT7 45
MUX2_LUT8 16
OBUF 7
RAM16SDP4 32
SPX9 4
VCC 1
I used your commands (almost) by writing them into a script (~/tmp/a.sh). The apicula version is Release 0.13 , the nextpnr version is master (releases are so rare that it almost never makes sense to use something other than the nextpnr master branch).
cd ~/src/apicula/examples/himbaechel
~/tmp/a.sh femto-riscv-18 >~/tmp/out.log 2>&1
a.sh:
#!/bin/sh
DEVICE='GW1NR-LV9QN88PC6/I5'
BOARD='tangnano9k'
BOARD_FREQ=27
CPU_FREQ=40
BAUD_RATE=115200
PROJECT=$1
# FIRMWARE='riscv-dsp-firmware/mult9x9.hex'
cat $0
#
yosys -DLEDS_NR=6 -DCPU_FREQ=$CPU_FREQ -DBAUD_RATE=$BAUD_RATE -DFIRMWARE=$FIRMWARE -DINV_BTN=0 -p "read_verilog $PROJECT.v; synth_gowin -json $PROJECT-$BOARD-synth.json"
nextpnr-himbaechel --json $PROJECT-$BOARD-synth.json --write $PROJECT-$BOARD-pnr.json --device $DEVICE --vopt family=GW1N-9C --vopt cst=$BOARD.cst
gowin_pack -d GW1N-9C -o pack.fs $PROJECT-$BOARD-pnr.json
sudo openFPGALoader -b $BOARD pack.fs